Why AAT-ITCH/OUCH

Faster time-to-market

Start from a working reference design: 10G Ethernet, feed handling, recovery and order entry are already integrated.

Sub-microsecond tick-to-trade

~574 ns wire-to-wire — market data in, order out, entirely in FPGA hardware.

See the latency breakdown →

Focus on your strategy

Write your strategy in HLS/C++ and replace the example order-book, pricing and order-entry blocks.

See the SMA demo →

Product Overview

This unified FPGA pipeline eliminates software jitter, reduces CPU load, and keeps tick-to-trade consistent at line rate.

System Block Diagram

🔍︎ Click to enlarge image

See AAT-ITCH/OUCH in Action

Watch on YouTube

Free evaluation demo: ready-to-run FPGA image, host software, market emulator and sample data — reference platform AMD Alveo X3522-PV.

Request demo

Market data in, order out, inside the FPGA

The ITCH/OUCH reference path runs entirely in hardware in ~574 ns — a sub-microsecond tick-to-trade.

~574ns

Rx + Tx protocol path

ITCH in over UDP · OUCH out over TCP · strategy excluded

Where the 574 ns goes

Rx 203

Tx 371

0 ns203574 ns

Reported by Design Gateway for the reference design, Sep 2026

⇡ UDP/TCP can be upgraded to Design Gateway IP — ask us

For engineers: where the 574 ns is spentRx 202.72 · Tx 371.0 · AAT IP Suite 85.3 ns details

Inside the 574 ns · how much is the AAT IP Suite itself

85.3

Network, transport & reference HLS blocks · 488.4Other blocks · 488.4

AAT IP Suite: Line + Feed 75.7 ns, TCP Handler 9.6 ns

Block by block

Same blocks as Design Gateway's latency figure. Select a block for details.

Rx latency ≈ 203 ns →

75.7 ns

AAT IP SuiteDesign Gateway

9.6 ns

← Tx latency ≈ 371 ns

Design Gateway IP Other blocks in the reference path (counted) Upgrade to Design Gateway IP available Your strategy (not counted)

Select any block to see what it does and how it contributes to the 574 ns.

Reported Rx + Tx path of the AAT IP Suite ITCH/OUCH reference design on AMD Alveo X3522-PV, running against an ASX Trade market emulator. The SMA pricing engine is user logic and is not part of the 574 ns. Per-block figures other than those shown are not published. Source: Design Gateway, AAT IP Suite newsletter, September 2026.

Demo strategy: SMA crossover, running on the FPGA

The demo ships with a complete trading strategy written in HLS C/C++. It reads live ITCH trades, decides on the FPGA, and sends real OUCH orders.

Trade Ticker from the market emulator: trade price with SMA(5) and SMA(20). Crossovers 1 and 3, where SMA(5) crosses above SMA(20), trigger BUY orders; crossovers 2 and 4, where it crosses below, trigger SELL orders. — BUY/SELL orders from the FPGA at each crossover · 🔍︎ click to enlarge

Each trade updates SMA(5) and SMA(20)
Fast crosses above slow → BUY
Fast crosses below slow → SELL

For engineers: how the reference Pricing Engine decides details

Fast SMA(5) and slow SMA(20) are averages of the latest 5 and 20 valid trade prices, updated on every valid trade.
Both become valid after 20 valid trade prices; the first non-equal relationship is stored as the starting point, and no order is sent for it.
An order is sent only when the relationship changes (a crossover). If the two averages are equal, nothing is sent and the previous relationship is kept.
The current trade price is used as the order price.
The engine is configured on the card with trade_on_card.cfg.
It is a reference block: replace it with your own C/C++ strategy and keep the network, protocol and order-entry path. It is not part of the reported ~574 ns.
New to HLS? Customized HLS training is available — ask us.

Features

Network

Hardware-Accelerated Network & Market Protocols

Ethernet, UDP/TCP and exchange protocols handled inside the FPGA.

Low-Latency Ethernet engine for wire-speed packet processing

TCP/UDP handled in hardware, avoiding kernel and driver overhead

ITCH decoder with integrated orderbook construction

Redundant A/B market-data feeds with filtering and missing-packet recovery

OUCH order-entry formatter for immediate order submission

MoldUDP64 over UDP multicast; SoupBinTCP over TCP for Glimpse and Order Entry

Built-in heartbeat and session-state logic for stable connectivity

Market State

Robust Market-State Management

A/B feed arbitration, Glimpse snapshot sync and gap recovery — in hardware.

Glimpse snapshot initialization to establish the initial order book

MoldUDP64 sequence-gap detection and missing-packet recovery (Line Handler)

Selectable gap-handling mode: high-reliability (buffer and recover) or low-latency (continue without gap recovery)

Line-rate hardware processing during high-throughput bursts

Strategy

Developer-Friendly Strategy Integration

Write your strategy in C/C++; the FPGA runs it.

HLS/C++ module for plugging in custom trading logic

Reduced development time compared to traditional RTL design

Reference strategy included — a Simple Moving Average (SMA) crossover (Fast SMA(5) vs Slow SMA(20)) — with sample PCAPs and replay utilities

Predefined test scenarios to accelerate evaluation and benchmarking

Reference design & integration support from Design Gateway

Specifications at a glance

Platform	AMD Alveo X3522-PV (reference demo) · other AMD FPGA platforms on request
Latency (reported)	~574 ns wire-to-wire · Rx 202.72 / Tx 371.0 ns · strategy logic excluded · breakdown
Protocols	ITCH / OUCH — NASDAQ-originated · demonstrated on ASX Trade, other ITCH/OUCH markets on request
Transport	MoldUDP64 (UDP multicast) · SoupBinTCP Glimpse & Order Entry (TCP)
Operating modes	Low-latency (continue without recovery) or high-reliability (buffer and recover)
Networking IP	Design Gateway Low-Latency IP Suite · UDP/TCP in HLS · full-suite upgrade on request
Connectivity	2× DSFP28 — up to 4× 10GbE (demo uses 2× 10GbE)
DMA / Driver	QDMA · QDMA DPDK
Toolchain / OS	Vivado 2022.1 · Ubuntu Server 22.04 LTS
Reference strategy	HLS/C++ Pricing Engine — SMA(5)/SMA(20) crossover
Field update	PCIe flash via xbflash2 — no JTAG cable required
Support	Reference design & integration support from Design Gateway

Documentation

Access comprehensive technical documentation, datasheets, and implementation guides for the Low-Latency Ethernet IP and AAT platform.

Demo Instruction Request Demo

Demo Documentation is currently under preparation. For early access, please contact us.

Free Demo is available upon request. Contact us to access the demo package.

Additional Resources

AAT-ITCH/OUCH — Solution OverviewWatch on YouTube ↗

From Software to FPGA — Full WalkthroughWatch on YouTube ↗

How to engage

Ready to evaluate or deploy?

Contact FinoLogic with your use-case, expected traffic profile, and target latency requirements.
Provide sample market data (anonymized) and reference trading scenarios.
We will review and propose an engagement plan (evaluation, pilot, or custom integration).

Contact Sales / Engineering

FAQ

What platforms are supported?

The reference demo runs on the AMD Alveo X3522-PV. The design can be ported to other AMD FPGA platforms — contact us with your target board.

Which exchanges are supported?

The protocols are NASDAQ-originated ITCH and OUCH. The reference demo is demonstrated on ASX Trade (against an ASX Trade market emulator), and the design can be adapted to ITCH/OUCH venues worldwide — contact us for your target market.

Can I integrate my own trading logic?

Yes. Write your strategy in HLS/C++ and replace the example Pricing Engine — see Developer-Friendly Strategy Integration.

What reference trading strategy is included?

An SMA(5)/SMA(20) crossover written in HLS C/C++ — see Demo strategy.

Do you provide reference designs?

Yes. The free evaluation package includes a ready-to-run FPGA image, host software, a market emulator and sample data. The full reference design comes with the licensed core, and can be built on the full Low-Latency IP Suite on request.

What about market data recovery?

Glimpse snapshot sync, A/B feed arbitration and MoldUDP64 gap recovery keep your order book in step with the market. A low-latency mode is also available that skips recovery for maximum speed.