Accelerated Algorithmic Trading (AAT)

Overview

The Starter Architecture combines Design Gateway's LL10GEMAC-IP with standard UDP/TCP functions and AMD QDMA. Pricing and trading logic remain on the host, keeping additional IP requirements and FPGA integration effort focused.

Performance Impact

LL10GEMAC-IP accelerates the Ethernet path, while PCIe transfers and host processing remain in the critical path.

Key Advantages

• Cost-conscious entry point among the four reference architectures.
• Adds DG low-latency Ethernet while retaining existing host software.
• Keeps additional IP requirements and FPGA integration scope focused.
• Provides a practical migration path to deeper FPGA acceleration.

Best For

Teams seeking a cost-conscious first step into FPGA-based trading acceleration while retaining their existing host-based pricing and trading software.

Overview

The reference architecture shown uses Calypte DMA by DYNANIC for ultra-low-latency transfers between the FPGA card and the host, together with Design Gateway's LL10GEMAC-IP for low-latency network access. Pricing and trading logic remain on the host. When required, the AAT IP Suite can be integrated into the AAT-Calypte FPGA design for customer-specific acceleration.

Performance Impact

Accelerating Ethernet and DMA removes part of the network and I/O software path, but PCIe transfers and host processing remain in the critical path.

Key Advantages

• Fast FPGA-to-host transfers for latency-sensitive host interaction.
• Keeps pricing and strategy software on the host in the reference configuration.
• Maintains customer control over system partitioning and integration.
• Supports AAT IP Suite integration when deeper FPGA acceleration is required.
• Provides an incremental path toward deeper FPGA acceleration.

Best For

Teams that want to retain host-based pricing and strategy software while preserving the option to add AAT IP Suite acceleration as requirements evolve.

Overview

Combines the AAT IP Suite with Design Gateway's Low-Latency IP Suite (LL-IPs), including LL10GEMAC-IP, UDP10GRx, and TOE10GLL. Together, these building blocks minimize the network and transport paths for market data and orders.

Performance Impact

Accelerating network, transport, AAT processing, and pricing minimizes the reference critical path and offers the highest latency-reduction potential among the four architectures.

Key Advantages

• Offers the highest latency-reduction potential among the four reference architectures.
• Minimizes the network and transport paths for market-data ingress and order egress.
• Pre-integrated AAT and DG low-latency IP building blocks reduce integration effort.
• Removes host dependency from the critical path when the pricing engine runs on-card.

Best For

Teams prioritizing the highest latency-reduction potential and ready to use the complete DG low-latency network and transport stack.