High-frequency trading on AMD Alveo

Accelerated Algorithmic Trading (AAT)

Accelerate High-Frequency Trading with the FinoLogic AAT Solution on FPGA, built on a market-proven ultra-low-latency IP foundation. The system receives real-time market data via UDP, processes it through a configurable pricing engine (deployable on-card or in host software), and executes orders via TCP, all while maintaining sub-microsecond latency.

FinoLogic's AAT solution supports multiple development flows and flexible pricing-engine deployment to reduce latency and shorten time-to-market. Select the flow that best fits your team— Vitis, QDMA, or Calypte —and scale seamlessly from prototype to production.

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10G EthernetPCIe DMASub-µs focusOn-card / Host pricing
Market data: UDPOrders: TCPMin. 2×10G links

Why Move from Host-Assisted SmartNIC to FPGA-Based Trading?

Compare a host-assisted NIC / SmartNIC architecture with FPGA-based AAT, where more of the latency-critical market-data and order path can move into hardware.

Conventional

Host-Assisted NIC / SmartNIC Architecture

Network functions are offloaded to the NIC or SmartNIC, while market-data processing, pricing, and trading logic remain primarily in host software.

  • Familiar setup for teams with existing NIC or SmartNIC infrastructure
  • Keeps pricing and strategy development in familiar CPU software
  • Useful as a baseline for latency and architecture comparison
  • Latency and customization depend on the host software path and selected NIC/SmartNIC ecosystem
Commercial consideration Vendor-specific software licenses, feature activation, and recurring support subscriptions may apply.
FPGA Accelerated

FPGA-Based AAT Architecture

FPGA-based AAT moves latency-critical market-data handling and order-path processing closer to the network while supporting host-assisted, hybrid, and on-card deployment architectures.

  • Lower and more deterministic latency than host-centered architectures
  • AAT IP Suite provides pre-built market-data and order-path processing
  • Pricing engine can remain on the host or move on-card depending on the latency target
  • Built for scalable migration from software-based trading to deeper FPGA acceleration
Commercial advantage A reusable, customer-defined FPGA architecture can reduce dependence on recurring SmartNIC platform and software fees. Selected FPGA IP licenses and support terms still apply.

Not sure which deployment architecture fits your latency and integration goals?

Talk to Our Engineers

Why AAT with FinoLogic

Market-proven Low-Latency IP

Low-Latency IP suite (Ethernet MAC IP Core, UDP/IP Offload IP Core, and TCP/IP Offload Engine (TOE) IP Core) delivers deterministic Ethernet/TCP/UDP paths optimized for exchange traffic.

Multiple development flows

Supports multiple development and integration flows — Vitis, QDMA, Calypte, and ITCH/OUCH — for different integration models, protocol requirements, latency targets, and pricing-engine placement.

Reference designs & docs

Complete reference designs for each supported development flow, accompanied by comprehensive documentation that clarifies the system and prepares you to integrate the pricing engine—whether on‑card or in host software.

How AAT Works: Architecture Overview

AAT connects host-side control, DMA data movement, FPGA-based trading logic, and the Ethernet subsystem into one low-latency trading path.

Accelerated Algorithmic Trading (AAT) Host System (Trader) Target System (Stock Market) CPU HW Config/ Control/Monitor DMA Driver PCIe FPGA DMA Engine Trading Engine (HLS) -User Module- Ethernet Subsystem 10GbE Market

Interactive block diagram — hover or tap the blocks for short descriptions.

Explore the AAT Solution Lineup

The architecture scenarios above connect to the supported AAT development flows below. Hybrid is based on AAT-Calypte and can integrate the AAT IP Suite when required, while Recommended and Complete use the AAT IP Suite as the core processing architecture and can be adapted to the appropriate development flow. Select multiple flows to compare.

What’s inside AAT

Networking IP

Ultra-low-latency Ethernet & transport.

LL10GEMAC-IP UDP10GRx TOE10GLL
Docs & downloads

DMA & Host stack

Choose the PCIe/host flow that fits your ops.

XDMA + XRT QDMA + QDMA DPDK Driver Calypte + NFB Driver

Target platforms

Deploy on AMD Alveo.

X3522 U50 U250 U55C Others on request

Deliverables & support

Reference design

Complete FPGA hardware projects with pre-integrated Ultra-Low-Latency IP cores, ready-to-build Vivado/Vitis projects, and example trading applications for supported Alveo platforms.

Documentation

Complete guides for system understanding and each flow with architecture details, build/run instructions.

Engineering support

Engage with FinoLogic engineers for integration, validation, and optimization best practices. For any questions or customization requirements, please contact us.

FAQ

Can the pricing engine run on the card?

Yes. Designs can place the pricing engine on-card (for lower latency by eliminating PCIe round-trips) or in host software (for flexibility and easier updates) depending on your specification or strategy requirements.

What protocols are supported?

Our design supports the FIX protocol (CME) and ITCH/OUCH (NASDAQ), with the system using UDP for market data reception and TCP for order execution. For different protocols or customized integrations, please contact us to discuss your specific requirements.

Success Stories

Thailand SET Market

FinoLogic partnered with a Thai trading company to deploy Alveo-based low-latency trading for the SET, delivering a production-proven system with validated market-data and order pipeline currently in live operation.

Market: SET Protocol: ITCH/OUCH Board: U50 On-card & Host options

Additional Resources

AAT Solution Overview

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